`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/31 12:58:38
// Design Name: 
// Module Name: execute
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module execute(
    clk,nop_b,data_1,data_2,rd_id,op_imm,imm_1,imm_2,imm_3,imm_4,data_2_exe,rd_exe,op_wr_id,op_wr_exe,op_rd_id,op_rd_exe,op_alu,op_b_id,
    op_j_id,op_b_exe,op_j_exe,addr_next_id,addr_next_exe,sex_imm,sex_imm_b,data_exe,zero,opcode_id,opcode_exe,data_fw_1,
    data_fw_2,rd_exe_fw,fw_1,fw_2
    );

    input clk,nop_b;
    input [31:0] data_1,data_2;
    input [4:0] rd_id;
    input [2:0] op_imm;
    input [4:0] imm_1;
    input [11:0] imm_2;
    input [6:0] imm_3;
    input [19:0] imm_4;
    input [1:0] op_wr_id;
    input [1:0] op_rd_id;
    input [2:0] op_alu;
    input op_j_id,op_b_id;
    input [31:0] addr_next_id;
    input [6:0] opcode_id;
    input [31:0] data_fw_1,data_fw_2;
    input [1:0] fw_1,fw_2;
    output [31:0] data_exe;
    output [31:0] sex_imm,sex_imm_b;
    output [31:0] data_2_exe;
    output reg [31:0] addr_next_exe;
    output reg [4:0] rd_exe;
    output reg [1:0] op_wr_exe;
    output reg [1:0] op_rd_exe;
    output [6:0] opcode_exe;
    output op_j_exe;
    output reg op_b_exe;
    output zero;
    output [4:0] rd_exe_fw;
    
    wire [31:0] data_imm;
    wire nop;
    
    assign op_j_exe = op_j_id;
    assign opcode_exe = opcode_id;
    assign rd_exe_fw = rd_id;

    always @(posedge clk) begin
        if(nop) begin
            rd_exe <= 5'bx;
            op_wr_exe <= 2'bx;
            op_rd_exe <= 2'bx;
            op_b_exe <= 1'b1;
            addr_next_exe <= 32'bx;
        end
        else begin
            rd_exe <= rd_id;
            op_wr_exe <= op_wr_id;
            op_rd_exe <= op_rd_id;
            op_b_exe <= op_b_id;
            addr_next_exe <= addr_next_id;
        end
    end

    extend_imm extend_imm(.clk(clk),.nop(nop_b),.op_imm(op_imm),.imm_1(imm_1),.imm_2(imm_2),.imm_3(imm_3),.imm_4(imm_4),.data_2(data_2),
    .data_imm(data_imm),.data_2_exe(data_2_exe),.sex_imm(sex_imm),.sex_imm_b(sex_imm_b));
    alu alu(.clk(clk),.nop(nop_b),.data_1(data_1),.data_2(data_imm),.op_alu(op_alu),.data_exe(data_exe),.zero(zero),.data_fw_1(data_fw_1),
    .data_fw_2(data_fw_2),.fw_1(fw_1),.fw_2(fw_2));
    
endmodule
